Messages in this thread | | | Date | Tue, 16 Sep 2014 19:50:15 -0700 | From | Nicolin Chen <> | Subject | Re: [PATCH] ASoC: fsl_spdif: don't change the root clock rate of spdif in driver |
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On Wed, Sep 17, 2014 at 10:31:28AM +0800, Shawn Guo wrote: > On Tue, Sep 16, 2014 at 07:24:40PM -0700, Nicolin Chen wrote: > > It's not supported in the clock API or just not implemented in our > > code? Can we just register a clock without CLK_SET_RATE_PARENT to > > achieve the purpose? (We are just trying to fix those PRED and PODF > > dividers when the driver calls set_rate to their GATE clock.) > > It seems I misunderstood your question. Yes, if we drop flag > CLK_SET_RATE_PARENT for the gate clock in question, the rate change > request will not be propagated to upstream dividers.
Okay. Since there's a solution that allows us to handle it better, problem solved then.
@Shengjiu Would you please take a look at the clock driver to implement a new clock register function? And make sure to register the GATE clock only without the flag CLK_SET_RATE_PARENT, as we may still need to set a reasonable rate for the clock by setting its PODF clock node instead.
Thank you both Nicolin
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