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    Subject[PATCH 3.2 039/131] MIPS: GIC: Prevent array overrun
    3.2.63-rc1 review patch.  If anyone has any objections, please let me know.

    ------------------

    From: Jeffrey Deans <jeffrey.deans@imgtec.com>

    commit ffc8415afab20bd97754efae6aad1f67b531132b upstream.

    A GIC interrupt which is declared as having a GIC_MAP_TO_NMI_MSK
    mapping causes the cpu parameter to gic_setup_intr() to be increased
    to 32, causing memory corruption when pcpu_masks[] is written to again
    later in the function.

    Signed-off-by: Jeffrey Deans <jeffrey.deans@imgtec.com>
    Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/7375/
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
    Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
    ---
    arch/mips/kernel/irq-gic.c | 6 ++++--
    1 file changed, 4 insertions(+), 2 deletions(-)

    --- a/arch/mips/kernel/irq-gic.c
    +++ b/arch/mips/kernel/irq-gic.c
    @@ -166,11 +166,13 @@ static void __init gic_setup_intr(unsign
    {
    /* Setup Intr to Pin mapping */
    if (pin & GIC_MAP_TO_NMI_MSK) {
    + int i;
    +
    GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
    /* FIXME: hack to route NMI to all cpu's */
    - for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
    + for (i = 0; i < NR_CPUS; i += 32) {
    GICWRITE(GIC_REG_ADDR(SHARED,
    - GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
    + GIC_SH_MAP_TO_VPE_REG_OFF(intr, i)),
    0xffffffff);
    }
    } else {


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