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    Subject[PATCH] perf/x86/uncore: export basic memory events for IVT IMC PMU

    This patch exposes two basic events for Ivytown IMC uncore PMU:

    - cas_count_read: number of full-cache line reads to memory controller
    - cas_count_write: number of full-cache line writes to memory controller

    Those events use the same encoding as for SNB-EP, so reuse the same
    event table. See specification in:

    http://www.intel.com/content/dam/www/public/us/en/documents/manuals/xeon-e5-2600-v2-uncore-manual.pdf

    By aggregating all the read and write events from all the memory controllers
    of each processor socket, one can determine the total memory bandwidth utilization.

    Signed-off-by: Stephane Eranian <eranian@google.com>
    ---
    arch/x86/kernel/cpu/perf_event_intel_uncore.c | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
    index cfc6f9d..800e087 100644
    --- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
    +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
    @@ -1391,6 +1391,7 @@ static struct intel_uncore_type ivt_uncore_imc = {
    .fixed_ctr_bits = 48,
    .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
    .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
    + .event_descs = snbep_uncore_imc_events,
    IVT_UNCORE_PCI_COMMON_INIT(),
    };

    --
    1.7.9.5


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