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SubjectRe: [PATCH V4 1/2] perf ignore LBR and extra_regs.
On Tue, Jul 08, 2014 at 09:49:40AM -0700, kan.liang@intel.com wrote:
> diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
> index 2bdfbff..f0e8022 100644
> --- a/arch/x86/kernel/cpu/perf_event.c
> +++ b/arch/x86/kernel/cpu/perf_event.c
> @@ -118,6 +118,9 @@ static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
> continue;
> if (event->attr.config1 & ~er->valid_mask)
> return -EINVAL;
> + /* Check if the extra msrs can be safely accessed*/
> + if (!x86_pmu.extra_msr_access[er->idx])
> + continue;

If you fail here;

> reg->idx = er->idx;
> reg->config = event->attr.config1;

> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index adb02aa..2be44be 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -1471,11 +1471,14 @@ static void intel_fixup_er(struct perf_event *event, int idx)
> {
> event->hw.extra_reg.idx = idx;
>
> - if (idx == EXTRA_REG_RSP_0) {
> + /* The extra_reg doesn't update if msrs cannot be accessed safely */
> + if ((idx == EXTRA_REG_RSP_0) &&
> + x86_pmu.extra_msr_access[EXTRA_REG_RSP_0]) {
> event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
> event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
> event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
> - } else if (idx == EXTRA_REG_RSP_1) {
> + } else if ((idx == EXTRA_REG_RSP_1) &&
> + x86_pmu.extra_msr_access[EXTRA_REG_RSP_1]) {
> event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
> event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
> event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;

You should never get here..

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