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SubjectRe: [PATCH 1/4] pinctrl: qpnp: Qualcomm PMIC pin controller driver
On Mon, Jul 07, 2014 at 06:11:30PM +0300, Ivan T. Ivanov wrote:

> +struct qpnp_pindesc {
> + u16 offset; /* address offset in SPMI device */
> + u32 index; /* offset from GPIO info base */
> + u8 type; /* peripheral hardware type */
> + u8 subtype; /* peripheral hardware subtype */
> + u8 major; /* digital major version */
> + u8 num_regs; /* control register count */
> + u8 cache[QPNP_NUM_CTL_REGS]; /* control register cache */
> +};

The device uses a regmap, why do you also need to open code a register
cache here?
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