Messages in this thread | | | Date | Thu, 17 Jul 2014 10:22:41 -0500 | From | Aravind Gopalakrishnan <> | Subject | Re: [PATCH] hwmon, k10temp: Add support for AMD F15h M60h processor |
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On 7/15/2014 4:03 AM, Guenter Roeck wrote: > On 07/15/2014 12:41 AM, Clemens Ladisch wrote: >> Guenter Roeck wrote: >>> On Mon, Jul 14, 2014 at 10:21:51PM +0200, Clemens Ladisch wrote: >>>> Borislav Petkov wrote: >>>>> On Mon, Jul 14, 2014 at 03:23:08PM -0500, Aravind Gopalakrishnan >>>>> wrote: >>>>>> + if (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model == >>>>>> 0x60) { >>>>>> + pci_bus_write_config_dword(pdev->bus, PCI_DEVFN(0, 0), >>>>>> + NB_SMU_IND_ADDR, IND_ADDR_OFFSET); >>>>>> + pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), >>>>>> + NB_SMU_IND_DATA, ®val); >>>> >>>> How do you prevent races with any other code that accesses some >>>> indirect >>>> register? >>>> >>> I just wanted to ask exactly the same question. I think this will need >>> locking. >> >> If there actually is any other code; these indirect SMU registers appear >> to be mostly undocumented and to be intended to be used by the BIOS. >> (Which makes me wonder why the temperature sensor was moved there.) >> > Scary. Does that mean there is a chance they may get used through ACPI ?
I have been asking internally about this, and looks like it's just a register address change. So we probably don't have to worry about this being used elsewhere..
> >> Anyway, if a lock is needed, it looks as if it could go into a helper >> function such as "amd_nb_smu_ind_read()" in arch/x86/kernel/amd_nb.c. >> > Yes, something like that. > > Okay, I shall add the locking mechanism and re-send.
Thanks, -Aravind.
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