Messages in this thread | | | Date | Mon, 30 Jun 2014 16:40:49 +0200 | From | Sebastian Hesselbarth <> | Subject | Re: [PATCH v7 1/7] phy: add a driver for the Berlin SATA PHY |
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On 06/30/2014 11:59 AM, Antoine Ténart wrote: > On Wed, Jun 25, 2014 at 11:03:25PM +0400, Sergei Shtylyov wrote: >> On 06/23/2014 05:39 PM, Antoine Ténart wrote: >>> + /* set the controller speed */ >>> + writel(0x31, ctrl_reg + PORT_SCR_CTL); >> >> Value undocumented? Or is this the SATA SControl register by chance? > > Some magic is still there...
Antoine,
I guess Sergei was referring to AHCI spec here. PORT_SCR bits are documented in AHCI spec as:
7:4 = 0x3 Limit speed negotiation to a rate not greater than Gen3 communication rate.
3:0 = 0x1 Perform interface communication sequence [...]. This is functionally equivalent to a hard reset [...].
So, the question is: Should we really need to reset controller in the PHY driver or is it already done in AHCI common code? At least we should change the comment to something like /* set Gen3 controller speed and perform hard reset */
Sebastian -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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