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SubjectRe: [PATCH v2] clk: exynos4: Add PPMU IP block source clocks.
On 27.05.2014 13:27, Jonghwa Lee wrote:
> Exynos4 has saveral PPMUs and each of them has operation clock which
> can be gated through CMU's SFR control.
>
> New clocks are listed below. All clocks are added as a gate-typed clock.
>
> CLK_PPMULEFT, CLK_PPMURIGHT, CLK_PPMUCAMIF, CLK_PPMUTV, CLK_PPMUMFC_L,
> CLK_PPMUMFC_R, CLK_G3D, CLK_PPMUIMAGE, CLK_PPMULCD0, CLK_PPMULCD1,
> CLK_PPMUFILE, CLK_PPMUGPS, CLK_PPMUDMC0, CLK_PPMUDMC1, CLK_PPMUCPU,
> CLK_PPMUACP,
>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Myungjoo Ham <myungjoo.ham@samsung.com>
> ---
> V2 :
> - Change clock definition order.
>
> drivers/clk/samsung/clk-exynos4.c | 19 +++++++++++++++++++
> include/dt-bindings/clock/exynos4.h | 18 ++++++++++++++++++
> 2 files changed, 37 insertions(+)

Applied for v3.17.

Best regards,
Tomasz


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