Messages in this thread Patch in this message | | | From | Stephane Eranian <> | Subject | [PATCH v2 2/2] perf/x86: load latency event supports all PEBS counters | Date | Fri, 27 Jun 2014 15:48:03 +0200 |
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This patch relaxes the event constraint for the Load Latency PEBS event on SNB/IVB/HSW. It was limited to counter 3 only for artificial reasons, i.e., to make scheduling it easier. This event uses an extra MSR which has to be shared among all events of a PMU. In Linux, there is a sophisticated infratstructure to handle shared regs, and we don't need to constrain the event to one counter.
The advantage of this patch is that it makes it possible to combine load latency and precise store events without multiplexing.
Signed-off-by: Stephane Eranian <eranian@google.com> --- arch/x86/kernel/cpu/perf_event_intel_ds.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index fdadec0..9dbfc9b 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -579,7 +579,7 @@ struct event_constraint intel_westmere_pebs_event_constraints[] = { struct event_constraint intel_snb_pebs_event_constraints[] = { INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ - INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ + INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ INTEL_PEBS_CONSTRAINT(0xf), /* catch all PEBS */ EVENT_CONSTRAINT_END @@ -587,7 +587,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = { struct event_constraint intel_ivb_pebs_event_constraints[] = { INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ - INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ + INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */ INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */ INTEL_PEBS_CONSTRAINT(0xf), /* catch all PEBS */ EVENT_CONSTRAINT_END @@ -596,7 +596,7 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = { struct event_constraint intel_hsw_pebs_event_constraints[] = { INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */ INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */ - INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.* */ + INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */ INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ INTEL_PEBS_CONSTRAINT(0xf), /* catch all PEBS */ EVENT_CONSTRAINT_END -- 1.7.9.5
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