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Subject[PATCH v2 0/3] Introduce ie31200_edac driver

Add support for memory errors for the Intel E3-1200 DRAM controllers.

While testing the driver, I found that doing a readq() on the
memory mapped memory controller hub registers caused a hard lockup
on my x86_64 system. It turns out that a read across a DW boundary
is a no no here.

Software must not access B0/D0/F0 32-bit memory-mapped registers with
requests that cross a DW boundary.

( p. 16)

Thus, I've added a generic lo_hi_[read|write]_q API, to deal with
this issue.

I think longer term the right thing is maybe to simply add these
definitions to include/asm-generic/io.h, as I didn't see any
in tree users of 'io-64-nonatomic-hi-lo.h', and simply remove
io-64-nonatomic-hi-lo.h and io-64-nonatomic-lo-hi.h. But I didn't want to
tie that cleanup to this edac driver submission.

I've been able to test this driver with a bad dimm on Sandy, Ivy Bridge and
Haswell systems, and it seems to be doing the right things, and populating
'/sys/devices/system/edac/mc/mc0/ue_count' correctly (which is what I really
care about).

I've tested:

CPU E3-1270 v3 @ 3.50GHz : 8086:0c08 (haswell)
CPU E3-1270 V2 @ 3.50GHz : 8086:0158 (ivy bridge)
CPU E31270 @ 3.40GHz : 8086:0108 (sandy bridge)

Posted before as:

Patch against 3.16.0-rc2



Changes since v1:
- Cleanups and formatting based on previous feedback

Jason Baron (3):
readq/writeq: Add explicit lo_hi_[read|write]_q and hi_lo_[read|write]_q
x38_edac: make use of lo_hi_readq()
ie31200_edac: Add driver

drivers/edac/Kconfig | 7 +
drivers/edac/Makefile | 1 +
drivers/edac/ie31200_edac.c | 542 ++++++++++++++++++++++++++++
drivers/edac/x38_edac.c | 15 +-
include/asm-generic/io-64-nonatomic-hi-lo.h | 14 +-
include/asm-generic/io-64-nonatomic-lo-hi.h | 14 +-
6 files changed, 574 insertions(+), 19 deletions(-)
create mode 100644 drivers/edac/ie31200_edac.c


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