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SubjectRe: [PATCHv6 1/3] devicetree: Addition of the Altera SDRAM controller
Hi!

On Fri, Jun 20, 2014 at 06:22:01PM -0500, tthayer@altera.com wrote:
> From: Thor Thayer <tthayer@altera.com>
>
> Addition of the Altera SDRAM Controller bindings and device tree changes.
>
> v2: Changes to SoC SDRAM EDAC code.
>
> v3: Implement code suggestions for SDRAM EDAC code.
>
> v4: Remove syscon from SDRAM controller bindings.
>
> v5: No Change, bump version for consistency.
>
> v6: Only map the ctrlcfg register as syscon.
>
> Signed-off-by: Thor Thayer <tthayer@altera.com>
> ---
> .../bindings/arm/altera/socfpga-sdram.txt | 11 +++++++++++
> arch/arm/boot/dts/socfpga.dtsi | 5 +++++
> 2 files changed, 16 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
> new file mode 100644
> index 0000000..5027026
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram.txt
> @@ -0,0 +1,11 @@
> +Altera SOCFPGA SDRAM Controller
> +
> +Required properties:
> +- compatible : "altr,sdr-ctl";
> +- reg : Should contain 1 register ranges(address and length)
> +
> +Example:
> + sdrctl@ffc25000 {
> + compatible = "altr,sdr-ctl";
> + reg = <0xffc25000 0x4>;
> + };
> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> index 4676f25..310292e 100644
> --- a/arch/arm/boot/dts/socfpga.dtsi
> +++ b/arch/arm/boot/dts/socfpga.dtsi
> @@ -682,6 +682,11 @@
> clocks = <&l4_sp_clk>;
> };
>
> + sdrctl@ffc25000 {
> + compatible = "altr,sdr-ctl", "syscon";

Did you forget to add the syscon to the binding documentation?

> + reg = <0xffc25000 0x4>;
> + };
> +
> rst: rstmgr@ffd05000 {
> compatible = "altr,rst-mgr";
> reg = <0xffd05000 0x1000>;

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