Messages in this thread | | | Date | Fri, 20 Jun 2014 10:21:34 +0530 | Subject | Re: [patch 1/2] clk: spear3xx: Use proper control register offset | From | Viresh Kumar <> |
| |
On Fri, Jun 20, 2014 at 3:22 AM, Thomas Gleixner <tglx@linutronix.de> wrote: > The control register is at offset 0x10, not 0x0. This is wreckaged > since commit 5df33a62c (SPEAr: Switch to common clock framework). > > Signed-off-by: Thomas Gleixner <tglx@linutronix.de> > Cc: stable@vger.kernel.org > --- > drivers/clk/spear/spear3xx_clock.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > Index: linux/drivers/clk/spear/spear3xx_clock.c > =================================================================== > --- linux.orig/drivers/clk/spear/spear3xx_clock.c > +++ linux/drivers/clk/spear/spear3xx_clock.c > @@ -211,7 +211,7 @@ static inline void spear310_clk_init(voi > /* array of all spear 320 clock lookups */ > #ifdef CONFIG_MACH_SPEAR320 > > -#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000) > +#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010) > #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) > > #define SPEAR320_UARTX_PCLK_MASK 0x1
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
| |