Messages in this thread | | | Date | Thu, 19 Jun 2014 13:56:24 -0700 | From | Andi Kleen <> | Subject | Re: [PATCH 2/2] perf/x86: fix constraints for load latency and precise events |
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On Thu, Jun 19, 2014 at 05:58:29PM +0200, Stephane Eranian wrote: > The load latency does not have to be constrained to counter 3 > on any of SNB, IVB, HSW. It operates fine on any PEBS-capable > counter. > > The precise store event for SNB, IVB needs to be on counter 3. > But on Haswell, precise store is implemented differently and > the constraint is not needed anymore, so we remove it.
Looks good to me.
-Andi
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