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SubjectRe: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles
On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> For all BG2Q SoCs, 2 cycles is the best/correct value

It would be a good idea to set all these parameters if you need to set
them at all - in other words, setting arm,dirty-latency as well, as
that's all part of the timing specification.

--
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improving, and getting towards what was expected from it.


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