Messages in this thread | | | Date | Thu, 12 Jun 2014 00:42:12 +0100 | From | Mark Brown <> | Subject | Re: [PATCH] spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI |
| |
On Wed, Jun 11, 2014 at 11:57:02PM +0800, Chew Chiau Ee wrote:
> It was observed that after module removal followed by insertion, > the SW mode chipselect is not properly set. Thus causing transfer > failure due to incorrect CS toggling.
> - value &= ~SPI_CS_CONTROL_SW_MODE; > + orig = value &= ~SPI_CS_CONTROL_SW_MODE; > writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL); > value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL); > if (value != orig) {
This is a *really* non-obvious fix, I'd have expected the original value to be re-read from the hardware here rather than just tweaked, or at least some comment explaining what's going on. Possibly also saving to a differently named temporary variable would do it but whatever I had to go look at the context to figure out what was happening and even there I was unclear. [unhandled content-type:application/pgp-signature] | |