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SubjectRe: [PATCH 1/5] x86, nmi: Add new nmi type 'external'
On Wed, May 07, 2014 at 06:27:46PM +0200, Ingo Molnar wrote:
> > [...] But I guess in theory, if a PMI NMI comes in and before the
> > cpu can accept it and GHES NMI comes in, then it would suffice to
> > say it may get dropped. That would be not be good. Though the race
> > would be very small.
> >
> > I don't have a good idea how to handle that.
>
> Well, are GHES NMIs reasserted if they are not handled? I don't know
> but there's a definite answer to that hardware behavior question.

I can't find anything that explicitly says the NMI will be re-asserted, so
I will it does not. Andi, do you know? (I am not sure who maintains GHES
any more).

>
> > On the flip side, we have the same exact problem, today, with the
> > other common external NMIs (SERR, IO). If a PCI SERR comes in at
> > the same time as a PMI, then it gets dropped. Worse, it doesn't get
> > re-enabled and blocks future SERRs (just found this out two weeks
> > ago because of a dirty perf status register on boot).
> >
> > Again, I don't have a solution to juggle between PMI performance and
> > reliable delivery. We could do away with the spinlocks and go back
> > to single cpu delivery (like it used to be). Then devise a
> > mechanism to switch delivery to another cpu upon hotplug.
> >
> > Thoughts?
>
> I'd say we should do a delayed timer that makes sure that all possible
> handlers are polled after an NMI is triggered, but never at a high
> rate.

Hmm, I was thinking about it and wanted to avoid a poll as I hear
complaints here and there about the nmi_watchdog constantly wasting power
cycles with its polling.

I was wondering if I could do a status read outside the spinlock, then if
a bit is set, just grab the spin_lock and re-read the status. But then
looking at the GHES code, I am not sure if it is as easy to read the
status bit as it is for a PCI_SERR/IO_CHK NMI.

Andi thoughts here? Should I poke Tony Luck?

Otherwise I can set up the polling if that doesn't work.

Cheers,
Don


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