lkml.org 
[lkml]   [2014]   [May]   [28]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold
> The only part I don't quite follow here is this:
> if (__test_and_set_bit(bit, (unsigned long *)&status))
> continue;
>
> Which seems to indicate the code is making sure each counter is
> processed only once. But it can only be processed once, if you have
> only one record. And if you have multiple, you want to be able to
> handle the same counter multiple times, at least once perf PEBS
> record. So I am a bit confused about this test.

Each PEBS record is only for a single counter overflow. So it
always should only be a single perf event.

-Andi


\
 
 \ /
  Last update: 2014-05-28 19:41    [W:3.159 / U:0.004 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site