Messages in this thread | | | Date | Wed, 28 May 2014 09:51:44 -0700 | From | Andi Kleen <> | Subject | Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold |
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> The only part I don't quite follow here is this: > if (__test_and_set_bit(bit, (unsigned long *)&status)) > continue; > > Which seems to indicate the code is making sure each counter is > processed only once. But it can only be processed once, if you have > only one record. And if you have multiple, you want to be able to > handle the same counter multiple times, at least once perf PEBS > record. So I am a bit confused about this test.
Each PEBS record is only for a single counter overflow. So it always should only be a single perf event.
-Andi
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