Messages in this thread |  | | Date | Mon, 19 May 2014 10:18:37 -0400 | | From | Don Zickus <> | | Subject | Re: [PATCH 6/6] perf: Add dcacheline sort |
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On Mon, May 19, 2014 at 03:34:14PM +0200, Jiri Olsa wrote: > On Fri, May 16, 2014 at 10:30:02AM -0400, Don Zickus wrote: > > On Fri, May 16, 2014 at 04:05:51PM +0200, Jiri Olsa wrote: > > > On Fri, May 16, 2014 at 09:30:58AM -0400, Don Zickus wrote: > > > > On Fri, May 16, 2014 at 01:47:57PM +0200, Jiri Olsa wrote: > > > > > On Tue, May 13, 2014 at 12:48:17PM -0400, Don Zickus wrote: > > > > > > In perf's 'mem-mode', one can get access to a whole bunch of details specific to a > > > > > > particular sample instruction. A bunch of those details relate to the data > > > > > > address. > > > > > > > > > > > > One interesting thing you can do with data addresses is to convert them into a unique > > > > > > cacheline they belong too. Organizing these data cachelines into similar groups and sorting > > > > > > them can reveal cache contention. > > > > > > > > > > > > This patch creates an alogorithm based on various sample details that can help group > > > > > > entries together into data cachelines and allows 'perf report' to sort on it. > > > > > > > > > > > > The algorithm relies on having proper mmap2 support in the kernel to help determine > > > > > > if the memory map the data address belongs to is private to a pid or globally shared. > > > > > > > > > > > > The alogortithm is as follows: > > > > > > > > > > > > o group cpumodes together > > > > > > o group entries with discovered maps together > > > > > > o sort on major, minor, inode and inode generation numbers > > > > > > o if userspace anon, then sort on pid > > > > > > o sort on cachelines based on data addresses > > > > > > > > > > needs some collumn width refresh or something..? ;-) > > > > > > > > Not sure what you mean here. > > > > > > > > > > > > > > # Overhead Data Cacheline > > > > > # ........ ....................... > > > > > > header not being wide enough to cover the longest data > > > > Ah. Ok. So I am not sure the right way to fix that. As the current > > header seems to be hardcoded with a bunch of spaces. Is there a trick to > > dynamically space it correctly based on the data provided? > > it should be enough to update function: > void hists__calc_col_len(struct hists *hists, struct hist_entry *h) > > with HISTC_MEM_DCACHELINE column update code, same as the rest
Ah, yes that worked perfectly. Will repost soon. :-)
Cheers, Don
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