lkml.org 
[lkml]   [2014]   [Apr]   [8]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: [PATCH 1/3] dts: socfpga: Add bindings for Altera SoC SDRAM controller
From
Date
On Tue, 2014-04-08 at 15:38 +0200, Steffen Trumtrar wrote:
> Hi!
>
> On Mon, Apr 07, 2014 at 04:54:07PM -0500, tthayer@altera.com wrote:
> > From: Thor Thayer <tthayer@altera.com>
> >
> > Addition of the Altera SDRAM controller bindings and device
> > tree changes to the Altera SoC project.
> >
[snip]
> > +
> > +Required properties:
> > +- compatible : "altr,sdr-ctl", "syscon";
> > + Note that syscon is invoked for this device to support the FPGA
> > + bridge driver, EDAC driver and other devices that share the
> > + registers.
> > +- reg : Should contain 1 register ranges(address and length)
>
> I haven't really thought this through, but why would the FPGA bridge driver
> access the sdram controller? For releasing the resets in fpgaportrst ? Or is
> there more?

Hi Steffan. No, not for resets. We need to enable the FPGA to SDRAM
path. Our SDRAM controller allows FPGA master access to the SDRAM.

> Wouldn't it be more appropriate to represent those bits as a reset-controller to
> some hypothetical IP core driver?
> Then you could have something like
>
> hps2fpga@c0000000 {
> ipcore@0 {
> resets = <&sdr 1>;
> reset-names = "foo";
> resets = <&rst 96>;
> reset-names = "bar";
> (...)
> };
>
> ipcore@1000 {
> resets = <&rst 96>;
> reset-names = "baz";
> (...)
> };
> };
>
> And you would always have the correct bridges released out of reset for your
> IP core. Does the FPGA bridge driver do more? I think that is basically it.
> Where we maybe could run into problems though is the early_init stuff.
>
> I think syscon is nice for some things, but we should try not to overuse it.

Understood. In this case, syscon seems to be appropriate.
>
> Regards,
> Steffen
>
> > +Example:
> > + sdrctl@ffc25000 {
> > + compatible = "altr,sdr-ctl", "syscon";
> > + reg = <0xffc25000 0x1000>;
> > + };
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index df43702..6ce912e 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -676,6 +676,11 @@
> > clocks = <&l4_sp_clk>;
> > };
> >
> > + sdrctl@ffc25000 {
> > + compatible = "altr,sdr-ctl", "syscon";
> > + reg = <0xffc25000 0x1000>;
> > + };
> > +
> > rstmgr@ffd05000 {
> > compatible = "altr,rst-mgr";
> > reg = <0xffd05000 0x1000>;
>



\
 
 \ /
  Last update: 2014-04-08 17:01    [W:0.103 / U:3.028 seconds]
©2003-2018 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site