Messages in this thread | | | Date | Tue, 8 Apr 2014 12:08:51 +0200 | From | Borislav Petkov <> | Subject | Re: [PATCH 3/3] edac: altera: Add SDRAM EDAC support for CycloneV/ArriaV |
| |
On Mon, Apr 07, 2014 at 04:54:09PM -0500, tthayer@altera.com wrote: > From: Thor Thayer <tthayer@altera.com> > > Added EDAC support for reporting ECC errors of CycloneV > and ArriaV SDRAM controller. > - The SDRAM Controller registers are used by the FPGA bridge so > these are accessed through the syscon interface. > - The configuration of the SDRAM memory size for the EDAC framework > is discovered from the memory node of the device tree. > - Documentation of the bindings in devicetree/bindings/arm/altera/ > socfpga-sdram-edac.txt > - Correction of single bit errors, detection of double bit errors.
Before I go and take a look at this further, is anyone at Altera going to maintain this driver in case of bug reports and issues with it?
Also, I see patch 3/3. Are the other two related? I see they are devicetree additions and, as such, all three should go together...
-- Regards/Gruss, Boris.
Sent from a fat crate under my desk. Formatting is fine. --
| |