Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 30 Apr 2014 13:29:46 +0100 | From | Lee Jones <> | Subject | Re: [RFC 07/47] mtd: nand: stm_nand_bch: initialise the BCH Controller |
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> >> >+ /* Reset and disable boot-mode controller */ > >> >+ writel(BOOT_CFG_RESET, nandi->base + NANDBCH_BOOTBANK_CFG); > >> >+ udelay(1); > >> >+ writel(0x00000000, nandi->base + NANDBCH_BOOTBANK_CFG); > >> > >> Why using 'udelay' ? > >> Isn't there any status register which tells you that controller is reset / initialized ? > >> Or may be polling on NANDBCH_BOOTBANK_CFG may itself give you status. > > > >Documenation says: > > > > "The soft reset bit has to be reset to ‘0’ to de-assert the soft > > reset. The soft reset bit is expected to be asserted for at least > > one clock cycle for proper reset" > > > That’s the hardware way of saying that 'enable the clock before applying reset'. > Clock is required to propagate reset-logic to flip-flops in pipeline, which do not get direct reset. > > However that apart. You may safely drop udelay(1) because this 'udelay' is at > CPU side and won't guarantee anything about clocks at your controller side. > But I leave it to you as this delay is pretty small.
I'd like to keep it in if it's all the same to you. The original author is pretty competent and I like to think that it's there for a reason - and as you rightly say, the delay is pretty small.
-- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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