On Sat, 26 Apr 2014, Sebastian Hesselbarth wrote:

> Non-DT irq handlers were working through irq causes from most-significant
> to least-significant bit, while DT irqchip driver does it the other way
> round. This revealed some more HW issues on Kirkwood peripheral IP, where
> spurious sdio irqs can happen although IP's irq enable registers are all
> zero. Although, not directly related with the described issue, reverse
> irq bit handling back to original order by replacing ffs() with fls().

So why are we reverting to the original order?

The explanation above is just confusing.

Thanks,

	tglx

> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
> Acked-by: Jason Cooper <jason@lakedaemon.net>
> ---
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Andrew Lunn <andrew@lunn.ch>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> ---
>  drivers/irqchip/irq-orion.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
> index e25f246cd2fb..34d18b48bb78 100644
> --- a/drivers/irqchip/irq-orion.c
> +++ b/drivers/irqchip/irq-orion.c
> @@ -42,7 +42,7 @@ __exception_irq_entry orion_handle_irq(struct pt_regs *regs)
>  		u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) &
>  			gc->mask_cache;
>  		while (stat) {
> -			u32 hwirq = ffs(stat) - 1;
> +			u32 hwirq = __fls(stat);
>  			u32 irq = irq_find_mapping(orion_irq_domain,
>  						   gc->irq_base + hwirq);
>  			handle_IRQ(irq, regs);
> @@ -117,7 +117,7 @@ static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
>  		   gc->mask_cache;
> 
>  	while (stat) {
> -		u32 hwirq = ffs(stat) - 1;
> +		u32 hwirq = __fls(stat);
> 
>  		generic_handle_irq(irq_find_mapping(d, gc->irq_base + hwirq));
>  		stat &= ~(1 << hwirq);
> -- 
> 1.9.1
> 
>