Messages in this thread | | | Date | Fri, 25 Apr 2014 11:31:49 -0500 | From | Timur Tabi <> | Subject | Re: [PATCH v3 1/1] pinctrl: add Intel BayTrail GPIO/pinctrl support |
| |
Rafael J. Wysocki wrote: >> > > I would be interested in understanding what exactly the flow is in that > situation, so care to educate me? What does the driver do to trigger > this and what exactly does happen in response to that?
I only just learned some of this myself, so I'm no expert. My understanding is that the all of the pinctrl-* properties and nodes are scanned by the pinctrl layer itself. So you could have a SATA controller node that points to a pin control node (via phandles). When the SATA driver is probed, the pinctrl layer notices the phandles and automatically calls the pinctrl layer to configure the pins and pin muxes.
-- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation.
| |