Messages in this thread | | | Date | Fri, 25 Apr 2014 06:51:47 -0700 | From | Guenter Roeck <> | Subject | Re: Microblaze image hanging in qemu with 3.15-rc |
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On 04/25/2014 06:29 AM, Guenter Roeck wrote: > On 04/25/2014 12:25 AM, Michal Simek wrote: > [ ... ] > >> >> It should be pretty easy to fix it in timer_write function like this. >> >> diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c >> index 6113b97..3ff1da9 100644 >> --- a/hw/timer/xilinx_timer.c >> +++ b/hw/timer/xilinx_timer.c >> @@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr, >> if (value & TCSR_TINT) >> value &= ~TCSR_TINT; >> >> - xt->regs[addr] = value; >> + xt->regs[addr] = value & 0x7ff; >> if (value & TCSR_ENT) >> timer_enable(xt); >> break; >> > > Hi Michal, > > that fixes endianness detection, but the image is still hanging. > > Here is the log: > > NR_IRQS:33 > /plb@0/interrupt-controller@81800000: num_irq=4, edge=0xa > ERROR: CPU CCF input clock not found > Reading TCSR0 returned 0x0, expected 0x1 > Switch to big endian mode > /plb@0/timer@83c00000: irq=1 > ERROR: timer CCF input clock not found > ERROR: Using CPU clock frequency > xilinx_timer_set_mode: shutdown > xilinx_timer_set_mode: periodic > sched_clock: 32 bits at 62MHz, resolution 16ns, wraps every 68719476720ns > Calibrating delay loop... QEMU: Terminated > > I added a couple of log messages to make sure that the mode is detected correctly. > Any idea what else might be wrong ? >
Never mind, I found it. Same problem with interrupt handler. Can you give me the valid bit mask for intc_baseaddr + MER ?
Thanks, Guenter
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