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Subject[PATCH 3.13 03/46] clocksource: vf_pit_timer: use complement for sched_clock reading
3.13-stable review patch.  If anyone has any objections, please let me know.


From: Stefan Agner <>

commit 224aa3ed45c8735ae02bb2ecca002409fa6aa772 upstream.

Vybrids PIT register is monitonic decreasing. However, sched_clock
reading needs to be monitonic increasing. Use bitwise not to get
the complement of the clock register. This fixes the clock going
backward. Also, the clock now starts at 0 since we load the
register with the maximum value at start.

Signed-off-by: Stefan Agner <>
Acked-by: Shawn Guo <>
Signed-off-by: Thomas Gleixner <>
Signed-off-by: Greg Kroah-Hartman <>

drivers/clocksource/vf_pit_timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/clocksource/vf_pit_timer.c
+++ b/drivers/clocksource/vf_pit_timer.c
@@ -54,7 +54,7 @@ static inline void pit_irq_acknowledge(v

static u64 pit_read_sched_clock(void)
- return __raw_readl(clksrc_base + PITCVAL);
+ return ~__raw_readl(clksrc_base + PITCVAL);

static int __init pit_clocksource_init(unsigned long rate)

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