Messages in this thread | | | From | David Laight <> | Subject | RE: [PATCH 9/9] powerpc/pm: support deep sleep feature on T1040 | Date | Fri, 21 Mar 2014 09:21:56 +0000 |
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From: Scott Wood [mailto:scottwood@freescale.com] > On Thu, 2014-03-20 at 11:59 +0000, David Laight wrote: > > I tried to work out what the 'twi, isync' instructions were for (in in_le32()). > > The best I could come up with was to ensure a synchronous bus-fault. > > But bus faults are probably only expected during device probing - not > > normal operation, and the instructions will have a significant cost. > > > > Additionally in_le32() and out_le32() both start with a 'sync' instruction. > > In many cases that isn't needed either - an explicit iosync() can be > > used after groups of instructions. > > The idea is that it's better to be maximally safe by default, and let > performance critical sections be optimized using raw accessors and > explicit synchronization if needed, than to have hard-to-debug bugs due > to missing/wrong sync. A lot of I/O is slow enough that the performance > impact doesn't really matter, but the brain-time cost of getting the > sync right is still there.
Hmmm....
That might be an excuse for the 'sync', but not the twi and isync.
I was setting up a dma request (for the ppc 83xx PCIe bridge) and was doing back to back little-endian writes into memory. I had difficulty finding and including header files containing the definitions for byteswapped accesses I needed. arch/powerpc/include/asm/swab.h contains some - but I couldn't work out how to get it included (apart from giving the full path).
In any case you need to understand when synchronisation is required - otherwise you will get it wrong. Especially since non-byteswapped accesses are done by direct access.
David
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