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SubjectRe: [PATCH v12 3/4] PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
Hi Balbi,

>> +/*
>> + * This function is used to configure the PHY to operation as either SATA Gen1
>> + * or Gen2 speed.
>> + */
>> +static void xgene_phy_sata_force_gen(struct xgene_phy_ctx *ctx,
>> + int lane, int gen)
> why do you need to *force* the generation ? Is this because of some
> silicon errata ? It almost seems like this should be done through link
> negotiation between both link partners.

You can call this as an errata or limitation of the underlying PHY IP.
As start, the PHY is configured with auto neg up to 6Gbps (or Gen3
speed). After link up, we will know whether it is Gen1 (1.5Gbps), Gen2
(3.0Gbps), or Gen3 (6.0Gbps). In order to ensure reliability, the PHY
needs to be configured at specified speed. For this reason and after
link up, the PHY is re-trained for the linked up speed.


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