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SubjectRe: [PATCH v2 4/4] pci: Add support for creating a generic host_bridge from device tree
On Thu, Feb 27, 2014 at 03:58:41PM +0000, Arnd Bergmann wrote:
> On Thursday 27 February 2014 14:13:22 Liviu Dudau wrote:
> >
> > It is useful for host bridge drivers as this is the only place where we store
> > the physical CPU address for the IO range. This is then needed when setting up the
> > translation registers. Also used when calling the pci_ioremap_io function that I'm
> > introducing in the AArch64 patches.
>
> I don't understand what translation windows you are talking about. Is this
> about how the PCI spaces are mapped into the CPU address space? If so, I
> would strongly recommend to have this handled by the boot loader before
> calling into the kernel. For ARM32, we have a lot of embedded systems
> that require the PCI host driver to set up those windows, but actually
> it would be much better to just have the firmware tell us what the setup
> is and that use that.

The AXI to PCI bridge that I'm using has a set of registers for doing address translation.
When it sees an AXI translation that matches the programmed translation window will
convert it into a PCI write using the PCI address base written in that translation window.
In other words you basically program the DT range into those address translation registers
and the bridge does the AXI to PCI conversion for you.

>
> > Whole patch is still under legal review, but the fragment for setting up the ATR looks
> > like this:
> >
> > list_for_each_entry(window, &bridge->windows, list) {
> > res = window->res;
> > offset = window->offset;
> > wsize = ilog2(resource_size(res)) - 1;
> >
> > if (resource_type(res) == IORESOURCE_MEM)
> > update_atr_entry(pp->base + ATR_REG_whatever,
> > res->start, /* CPU address */
> > res->start - offset, /* PCI address */
> > 0, wsize);
> > else if (resource_type(res) == IORESOURCE_IO) {
> > io_offset = pci_ioremap_io(res, bridge->io_base + offset);
> > update_atr_entry(pp->base + ATR_REG_whatever,
> > bridge->io_base + res->start + offset, /* CPU address */
> > res->start, /* PCI address */
> > 0x20000, wsize);
> > }
> > }
>
> Hmm, I again don't see how 'bridge->io_base + res->start + offset' is
> the correct address here. What is it you are trying to pass into
> update_atr_entry()?

The physical CPU address where the IO range starts.

For IO:
res->start = beginning of logical I/O port block
offset = window->offset = res->start - range.pci_addr
bridge->io_base = range.cpu_addr

bridge->io_base + res->start + offset = range.cpu_addr + res->start + res->start - range.pci_addr

Hmm, writting code without coffee .... :)

Lucky for me res->start = range.pci_addr = 0, but I can see now where I've got it wrong. Thanks!

Liviu

>
> Arnd
>
>

--
====================
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| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
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