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    Subject[PATCH] ASoC: fsl-sai: Add SND_SOC_DAIFMT_DSP_A/B support.
    Date
    o Add SND_SOC_DAIFMT_DSP_A support.
    o Add SND_SOC_DAIFMT_DSP_B support.

    Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
    ---
    sound/soc/fsl/fsl_sai.c | 45 ++++++++++++++++++++++++++++++++++++++++++---
    sound/soc/fsl/fsl_sai.h | 1 +
    2 files changed, 43 insertions(+), 3 deletions(-)

    diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
    index 26d9f5e..c4a4231 100644
    --- a/sound/soc/fsl/fsl_sai.c
    +++ b/sound/soc/fsl/fsl_sai.c
    @@ -108,15 +108,44 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
    /* DAI mode */
    switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
    case SND_SOC_DAIFMT_I2S:
    - /* Data on rising edge of bclk, frame low, 1clk before data */
    + /*
    + * Frame low, 1clk before data, one word length for frame sync,
    + * frame sync starts one serial clock cycle earlier,
    + * that is, together with the last bit of the previous
    + * data word.
    + */
    val_cr2 &= ~FSL_SAI_CR2_BCP;
    val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
    break;
    case SND_SOC_DAIFMT_LEFT_J:
    - /* Data on rising edge of bclk, frame high, 0clk before data */
    + /*
    + * Frame high, one word length for frame sync,
    + * frame sync asserts with the first bit of the frame.
    + */
    val_cr2 &= ~FSL_SAI_CR2_BCP;
    val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
    break;
    + case SND_SOC_DAIFMT_DSP_A:
    + /*
    + * Frame high, 1clk before data, one bit for frame sync,
    + * frame sync starts one serial clock cycle earlier,
    + * that is, together with the last bit of the previous
    + * data word.
    + */
    + val_cr2 &= ~FSL_SAI_CR2_BCP;
    + val_cr4 &= ~FSL_SAI_CR4_FSP;
    + val_cr4 |= FSL_SAI_CR4_FSE;
    + sai->is_dsp_mode = true;
    + break;
    + case SND_SOC_DAIFMT_DSP_B:
    + /*
    + * Frame high, one bit for frame sync,
    + * frame sync asserts with the first bit of the frame.
    + */
    + val_cr2 &= ~FSL_SAI_CR2_BCP;
    + val_cr4 &= ~(FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP);
    + sai->is_dsp_mode = true;
    + break;
    case SND_SOC_DAIFMT_RIGHT_J:
    /* To be done */
    default:
    @@ -219,7 +248,9 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
    val_cr5 &= ~FSL_SAI_CR5_W0W_MASK;
    val_cr5 &= ~FSL_SAI_CR5_FBT_MASK;

    - val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
    + if (!sai->is_dsp_mode)
    + val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
    +
    val_cr5 |= FSL_SAI_CR5_WNW(word_width);
    val_cr5 |= FSL_SAI_CR5_W0W(word_width);

    @@ -245,6 +276,10 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
    struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
    u32 tcsr, rcsr;

    + /*
    + * The transmitter bit clock and frame sync are to be
    + * used by both the transmitter and receiver.
    + */
    regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
    ~FSL_SAI_CR2_SYNC);
    regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
    @@ -261,6 +296,10 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
    tcsr &= ~FSL_SAI_CSR_FRDE;
    }

    + /*
    + * It is recommended that the transmitter is the last enabled
    + * and the first disabled.
    + */
    switch (cmd) {
    case SNDRV_PCM_TRIGGER_START:
    case SNDRV_PCM_TRIGGER_RESUME:
    diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
    index 1571459..e432260 100644
    --- a/sound/soc/fsl/fsl_sai.h
    +++ b/sound/soc/fsl/fsl_sai.h
    @@ -103,6 +103,7 @@ struct fsl_sai {

    bool big_endian_regs;
    bool big_endian_data;
    + bool is_dsp_mode;

    struct snd_dmaengine_dai_dma_data dma_params_rx;
    struct snd_dmaengine_dai_dma_data dma_params_tx;
    --
    1.8.4



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