Messages in this thread Patch in this message | | | Date | Fri, 21 Feb 2014 13:14:19 -0800 | From | tip-bot for Peter Zijlstra <> | Subject | [tip:perf/urgent] perf/x86: Correctly use FEATURE_PDCM |
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Commit-ID: c9b08884c9c98929ec2d8abafd78e89062d01ee7 Gitweb: http://git.kernel.org/tip/c9b08884c9c98929ec2d8abafd78e89062d01ee7 Author: Peter Zijlstra <peterz@infradead.org> AuthorDate: Mon, 3 Feb 2014 14:29:03 +0100 Committer: Thomas Gleixner <tglx@linutronix.de> CommitDate: Fri, 21 Feb 2014 22:09:01 +0100
perf/x86: Correctly use FEATURE_PDCM
The current code simply assumes Intel Arch PerfMon v2+ to have the IA32_PERF_CAPABILITIES MSR; the SDM specifies that we should check CPUID[1].ECX[15] (aka, FEATURE_PDCM) instead.
This was found by KVM which implements v2+ but didn't provide the capabilities MSR. Change the code to DTRT; KVM will also implement the MSR and return 0.
Cc: pbonzini@redhat.com Reported-by: "Michael S. Tsirkin" <mst@redhat.com> Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20140203132903.GI8874@twins.programming.kicks-ass.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de> --- arch/x86/kernel/cpu/perf_event_intel.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 698ae77..aa333d9 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2308,10 +2308,7 @@ __init int intel_pmu_init(void) if (version > 1) x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); - /* - * v2 and above have a perf capabilities MSR - */ - if (version > 1) { + if (boot_cpu_has(X86_FEATURE_PDCM)) { u64 capabilities; rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
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