Messages in this thread | | | Date | Thu, 6 Nov 2014 12:54:25 +0800 | From | Yijing Wang <> | Subject | Re: [Patch Part2 v4 21/31] PCI/MSI: enhance PCI MSI core to support hierarchy irqdomain |
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On 2014/11/6 12:10, Bjorn Helgaas wrote: > On Wed, Nov 5, 2014 at 6:58 PM, Yijing Wang <wangyijing@huawei.com> wrote: > >>>> +{ >>>> + return (irq_hw_number_t)msidesc->msi_attrib.entry_nr | >>>> + PCI_DEVID(pdev->bus->number, pdev->devfn) << 11 | >>>> + (pci_domain_nr(pdev->bus) & 0xFFFFFFFF) << 27; >>> >>> Where does this bit layout come from? Is this defined in the spec >>> somewhere? A reference would help. >> >> Currently, more and more Non-PCI device use MSI(or similar MSI mechanism), like DMAR fault irq >> and HPET FSB irq. And we have to add additional code to support the MSI capability. >> So I hope we can decouple MSI code and PCI code, then we can unify all MSI(or Message Based interrupt) >> in one framework. > > Was that supposed to answer my question? If so, I didn't understand > how it explains where the bit layout came from.
No, that's just my concern. Because this function uses the pci device id, but more and more Non-PCI devices use MSI.
> > Bjorn > -- > To unsubscribe from this list: send the line "unsubscribe linux-acpi" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > > . >
-- Thanks! Yijing
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