Messages in this thread Patch in this message | | | From | Kevin Cernekee <> | Subject | [PATCH V2 13/22] MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizes | Date | Sat, 15 Nov 2014 16:17:37 -0800 |
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CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However, it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the L1_SHIFT selection into the CPU or SoC section so that other SoCs can select different values.
Signed-off-by: Kevin Cernekee <cernekee@gmail.com> --- arch/mips/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 92033b7..3d56928 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -326,6 +326,7 @@ config MIPS_MALTA select I8259 select MIPS_BONITO64 select MIPS_CPU_SCACHE + select MIPS_L1_CACHE_SHIFT_6 select PCI_GT64XXX_PCI0 select MIPS_MSC select SWAP_IO_SPACE @@ -1909,7 +1910,6 @@ config IP22_CPU_SCACHE config MIPS_CPU_SCACHE bool select BOARD_SCACHE - select MIPS_L1_CACHE_SHIFT_6 config R5000_CPU_SCACHE bool -- 2.1.1
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