lkml.org 
[lkml]   [2014]   [Nov]   [14]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH v11 09/12] drm: bridge/dw_hdmi: clear i2cmphy_stat0 reg in hdmi_phy_wait_i2c_done
    Date
    HDMI_IH_I2CMPHY_STAT0 is a clear on write register, which indicates i2cm
    operation status(i2c transfer done or error), every hdmi phy register
    configuration must check this register to make sure the configuration
    has complete. But the indication bit should be cleared after check, otherwise
    the corresponding bit will hold on forever, this may give a wrong signal for
    next check.

    Signed-off-by: Andy Yan <andy.yan@rock-chips.com>

    ---

    Changes in v11:
    - split form patch <dw_hdmi: add rk3288 support>

    Changes in v10: None
    Changes in v9: None
    Changes in v8: None
    Changes in v7: None
    Changes in v6: None
    Changes in v5: None
    Changes in v4: None
    Changes in v3: None
    Changes in v2: None

    drivers/gpu/drm/bridge/dw_hdmi.c | 6 +++++-
    1 file changed, 5 insertions(+), 1 deletion(-)

    diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c
    index e94f6bb..d5d5207 100644
    --- a/drivers/gpu/drm/bridge/dw_hdmi.c
    +++ b/drivers/gpu/drm/bridge/dw_hdmi.c
    @@ -668,11 +668,15 @@ static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,

    static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
    {
    - while ((hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
    + u32 val;
    +
    + while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
    if (msec-- == 0)
    return false;
    udelay(1000);
    }
    + hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
    +
    return true;
    }

    --
    1.9.1


    \
     
     \ /
      Last update: 2014-11-14 15:21    [W:4.664 / U:0.100 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site