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SubjectRE: phy/micrel: KSZ8031RNL RMII clock reconfiguration bug
Hi Johan,

> As you may have seen by now, I've been working on refactoring the micrel phy driver to be able to use common initialisation code.
> Specifically, I've added generic support for disabling the broadcast address, which is what the MII_KSZPHY_OMSO write above does.
> Generally you want this to be the first thing you do in order to avoid unnecessary reconfigurations. If we ever were to allow concurrent probing this would also be a requirement.
> Could you provide some detail about the setup were you find that the PHY becomes unresponsive without your patch? Do you have more than one PHY on the bus? Using what addresses? And using what clock modes (i.e. 25 MHz or 50 MHz)?
> Also, what exactly do you mean by "unresponsive"? Are you still able to read the PHY registers for example?

I think it sounds like a good idea to refactor the init code.

My setup:
iMX28 processor with dual Ethernet MAC; FEC0 (enabled) and FEC1 (disabled).
There is a single KSZ8031 PHY that receives 50MHz RMII clock from the MAC.
I am unable to read PHY registers from both user-land tools and extra debug PHY reads in driver code.

Boot trace:
[ 22.277785] fec 800f0000.ethernet eth0: Freescale FEC PHY driver [Micrel KSZ8031] (mii_bus:phy_addr=800f0000.etherne:00, irq=-1)
[ 22.292527] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[ 24.276217] libphy: 800f0000.etherne:00 - Link is Up - 100/Full
[ 24.285094] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

Venlig hilsen / Best regards

Kamstrup A/S <>
Bruno Thomsen
Development engineer

Kamstrup A/S
Industrivej 28
DK-8660 Skanderborg
Tel: +45 89 93 10 00
Fax: +45 89 93 10 01
Dir: +45 89 93 13 94

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