[lkml]   [2014]   [Nov]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH v3 1/2] x86, mce, severity: extend the the mce_severity mechanism to handle UCNA/DEFERRED error
On Mon, Nov 10, 2014 at 11:32:12PM +0000, Luck, Tony wrote:
> But then I tested it ...
> I injected a UC error to memory - then did a simple byte write to the target line.
> This resulted in two banks logging errors:
> [ 124.638045] poll: CPU54 saw ec00000000010092 in bank 7
> [ 124.639006] poll: severity = 0
> [ 124.647333] poll: CPU54 saw b800000000200179 in bank 3
> [ 124.648322] poll: severity = 1
> The bank 7 error reported as severity 0 because EN=0 ... so we took no action for it.

How come EN is 0? Bank7 error reporting is not enabled? Why? Or the
error injection thing doesn't do it?

> The bank 3 error got past that hurdle, then through the next BIT(8) set indicates a
> cache error. Fell at the last check because ADDRV=0.

I guess you could tweak the injection path to write in a default address
so that that check gets bypassed...

> I think the severity table entry for the "EN" check should have been skipped
> when calling from the CMCI handler. Then we would have seen severity=1
> from the bank 7 error. It would have passed the other tests too (BIT(7) and

... but this is yet another example that this severity table is hard to
extend and handle.


Sent from a fat crate under my desk. Formatting is fine.

 \ /
  Last update: 2014-11-11 10:41    [W:0.092 / U:18.416 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site