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SubjectRe: [PATCH] n_tty: Add memory barrier to fix race condition in receive path
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Hi Måns,

On Mon, Nov 10, 2014 at 10:25 AM, Måns Rullgård <mans@mansr.com> wrote:
> Christian Riesch <christian.riesch@omicron.at> writes:
>
>> On Thu, Nov 6, 2014 at 9:56 PM, Greg Kroah-Hartman
>> <gregkh@linuxfoundation.org> wrote:
>>> On Thu, Nov 06, 2014 at 08:49:01PM +0000, Måns Rullgård wrote:
>>>> Greg Kroah-Hartman <gregkh@linuxfoundation.org> writes:
>>>>
>>>> > On Thu, Nov 06, 2014 at 12:39:59PM +0100, Christian Riesch wrote:
>>>> >> The current implementation of put_tty_queue() causes a race condition
>>>> >> when re-arranged by the compiler.
>>>> >>
>>>> >> On my build with gcc 4.8.3, cross-compiling for ARM, the line
>>>> >>
>>>> >> *read_buf_addr(ldata, ldata->read_head++) = c;
>>>> >>
>>>> >> was re-arranged by the compiler to something like
>>>> >>
>>>> >> x = ldata->read_head
>>>> >> ldata->read_head++
>>>> >> *read_buf_addr(ldata, x) = c;
>>>> >>
>>>> >> which causes a race condition. Invalid data is read if data is read
>>>> >> before it is actually written to the read buffer.
>>>> >
>>>> > Really? A compiler can rearange things like that and expect things to
>>>> > actually work? How is that valid?
>>>>
>>>> This is actually required by the C spec. There is a sequence point
>>>> before a function call, after the arguments have been evaluated. Thus
>>>> all side-effects, such as the post-increment, must be complete before
>>>> the function is called, just like in the example.
>>>>
>>>> There is no "re-arranging" here. The code is simply wrong.
>>>
>>> Ah, ok, time to dig out the C spec...
>>>
>>> Anyway, because of this, no need for the wmb() calls, just rearrange the
>>> logic and all should be good, right? Christian, can you test that
>>> instead?
>>
>> I ran a test with the patch that I posted in my first email for the
>> last 4 days. No communication errors occurred so the patch actually
>> fixes my problem. I will run another test as suggested by Greg, just
>> with rearranging the logic.
>
> What hardware are you running on? If it's a single-processor system,
> it won't break without barriers even if they are required for SMP.

Yes, single processor. Texas Instruments AM1808 SoC.

Thanks,
Christian
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