Messages in this thread | | | Date | Wed, 1 Oct 2014 11:04:24 -0700 | From | Sören Brinkmann <> | Subject | Re: [PATCH] staging: Add Xilinx Clocking Wizard driver |
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On Wed, 2014-10-01 at 10:57AM -0700, Greg Kroah-Hartman wrote: > On Wed, Oct 01, 2014 at 10:46:16AM -0700, Sören Brinkmann wrote: > > On Wed, 2014-10-01 at 10:39AM -0700, Greg Kroah-Hartman wrote: > > > On Wed, Oct 01, 2014 at 10:21:48AM -0700, Soren Brinkmann wrote: > > > > Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard > > > > provides an AXI interface to dynamically reconfigure the clocking > > > > resources of Xilinx FPGAs. > > > > > > Why not just do the few things you have on the TODO list and get it > > > merged to the "proper" part of the kernel, keeping it out of the staging > > > tree? > > > > The few things are not that easy and as I mention in the TODO file, > > there are some patches on LKML that would greatly simplify this > > driver/reduce the need for code duplication. > > I thought this is a good way to wait for those parts to mature while > > people could already use the driver as passive part in their clock tree. > > Ok, fair enough, as long as you keep working on the driver to get it out > of staging, I don't have an objection to it. I'll go queue it up later > today.
Thank you.
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