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    SubjectRe: [PATCH RFC 2/3] ARM: kernel: add support for cpu cache information
    On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote:
    > +#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */
    > +
    > +#define MAX_CACHE_LEVEL 1 /* Only 1 level supported */
    > +#define CTR_CTYPE_SHIFT 24
    > +#define CTR_CTYPE_MASK (1 << CTR_CTYPE_SHIFT)
    > +
    > +static inline unsigned int get_ctr(void)
    > +{
    > + unsigned int ctr;
    > + asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
    > + return ctr;
    > +}
    > +
    > +static enum cache_type get_cache_type(int level)
    > +{
    > + if (level > MAX_CACHE_LEVEL)
    > + return CACHE_TYPE_NOCACHE;
    > + return get_ctr() & CTR_CTYPE_MASK ?
    > + CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;

    So, what do we do for CPUs that don't implement the CTR? Just return
    random rubbish based on decoding the CPU Identity register as if it
    were the cache type register?

    --
    FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
    in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
    Estimate before purchase was "up to 13.2Mbit".


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