Messages in this thread | | | Subject | Re: [PATCH RFC] reciprocal_divide: correction/update of the algorithm | From | Eric Dumazet <> | Date | Tue, 14 Jan 2014 11:50:32 -0800 |
| |
On Tue, 2014-01-14 at 14:22 -0500, Austin S Hemmelgarn wrote:
> I disagree with the statement that current CPU's have reasonably fast > dividers. A lot of embedded processors and many low-end x86 CPU's do > not in-fact have any hardware divider, and usually provide it using > microcode based emulation if they provide it at all. The AMD Jaguar > micro-architecture in particular comes to mind, it uses an iterative > division algorithm provided by the microcode that only produces 2 bits > of quotient per cycle, even in the best case (2 8-bit integers and an > integral 8-bit quotient) this still takes 4 cycles, which is twice as > slow as any other math operation on the same processor.
I doubt you run any BPF filter with a divide instruction in it on these platform.
Get real, do not over optimize things where it does not matter.
| |