Messages in this thread Patch in this message | | | From | Will Deacon <> | Subject | [RFC PATCH 2/4] x86: cmpxchg: implement dummy cmpxchg64_relaxed operation | Date | Thu, 26 Sep 2013 16:13:29 +0100 |
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cmpxchg64_relaxed can be used to provide barrier-less semantics for a 64-bit cmpxchg operation in cases where the strong memory ordering is not required. A useful use-case for this is in the recently merged lockless lockref code.
This patch implements a dummy implementation for x86, since the memory ordering issues aren't a concern for this architecture.
Cc: <x86@kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> --- arch/x86/include/asm/cmpxchg.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h index d47786a..aacb99a0 100644 --- a/arch/x86/include/asm/cmpxchg.h +++ b/arch/x86/include/asm/cmpxchg.h @@ -152,6 +152,9 @@ extern void __add_wrong_size(void) #define cmpxchg_local(ptr, old, new) \ __cmpxchg_local(ptr, old, new, sizeof(*(ptr))) + +#define cmpxchg64_relaxed(ptr, old, new) \ + cmpxchg64(ptr, old, new) #endif /* -- 1.8.2.2
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