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SubjectRe: [PATCH 3/6] clk: exynos5250: add clock ID for div_pcm0
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Hi Andrew,

On Friday 20 of September 2013 14:13:54 Andrew Bresticker wrote:
> There is no gate for the PCM clock input to the AudioSS block, so
> the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that
> we can reference it in device trees.
>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> ---
> Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 +
> drivers/clk/samsung/clk-exynos5250.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz



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