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SubjectRe: /sys rules Re: [RFC PATCH] fpga: Introduce new fpga subsystem
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On Thu, 2013-09-19 at 07:18 -0700, Greg KH wrote:
> On Thu, Sep 19, 2013 at 04:10:46PM +0200, Michal Simek wrote:
> > On 09/19/2013 04:06 PM, Greg KH wrote:
> > > On Thu, Sep 19, 2013 at 02:52:37PM +0200, Pavel Machek wrote:
> > >> On Thu 2013-09-19 13:22:00, Michal Simek wrote:
> > >>> On 09/19/2013 01:17 PM, Pavel Machek wrote:
> > >>
> > >>>>> Status is just there and for my zynq devcfg driver I do export some status
> > >>>>> bits.
> > >>>>>
> > >>>>> root@petalinux:~# cat /sys/class/fpga/fpga0/status
> > >>>>> partial_bitstream_status: 0
> > >>>>> prog_done_status: 1
> > >>>>> dbg_lock_status: 0
> > >>>>> seu_lock_status: 0
> > >>>>> aes_en_lock_status: 0
> > >>>>> aes_status: 0
> > >>>>> seu_status: 0
> > >>>>> spniden_status: 1
> > >>>>> spiden_status: 1
> > >>>>> niden_status: 1
> > >>>>> dbgen_status: 1
> > >>>>> dap_en_status: 7
> > >>>>
> > >>>> This is single file? If so, it needs to be changed. Greg is rather
> > >>>> clear about that.
> > >>>
> > >>> Don't you have a link to these rules? I have seen any paragraph from Greg
> > >>> about it but I forget where was it.
> > >>
> > >> "one value per file" and "there must be documentation in
> > >> Documentation/ for each file" are the rules, iirc.
> > >>
> > >> There's Documentation/sysfs-rules.txt, but it does not seem too
> > >> relevant.
> > >
> > > Documentation/filesystems/sysfs.txt says it. It probably should be
> > > added to sysfs-rules.txt as well, but the odds that anyone ever reads
> > > the documentation is so low I doubt it's even worth it.
> > >
> > > Also, all sysfs files have to be documented in Documentation/ABI/ which
> > > this patch does not do :(
> > >
> > > And yes, multiple values in a single sysfs file is not allowed at all.
> > >
> >
> > ok. I will read that. This is output from my fpga end driver - nothing
> > what I have sent for review.
> > Can you please look at origin patch and tell me what you think about it?
>
> When I return from LinuxCon/Plumbers and catch up on my pending patch
> queue, I will. It seems that others have already provided good code
> review, so I suggest sending out a new version with their changes
> integrated and not wait for me.

Michal,

I am currently porting my altera fpga driver to work with your changes.
Please go ahead and post your xilinx fpga driver patch, that would help
accelerate my testing and give us a chance to give more feedback quickly
and arrive a satisfactory solution that will work for more of the key
players here.

Thanks,
ALan

>
> thanks,
>
> greg k-h
>




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