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Subject[PATCH] x86: add pin control support to Intel low power subsystem
Date
x86 chips with LPSS (low power subsystem) such as Lynxpoint and
Baytrail have SoC like peripheral support and controllable pins.

At the moment, Baytrail needs the pinctrl-baytrail driver to let
peripherals control their gpio resources, but more pincontrol functions
such as pin muxing and grouping are possible to add later.

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
---
arch/x86/Kconfig | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 30c40f0..91f72b5 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -482,11 +482,12 @@ config X86_INTEL_LPSS
bool "Intel Low Power Subsystem Support"
depends on ACPI
select COMMON_CLK
+ select PINCTRL
---help---
Select to build support for Intel Low Power Subsystem such as
found on Intel Lynxpoint PCH. Selecting this option enables
- things like clock tree (common clock framework) which are needed
- by the LPSS peripheral drivers.
+ things like clock tree (common clock framework) and pincontrol
+ which are needed by the LPSS peripheral drivers.

config X86_RDC321X
bool "RDC R-321x SoC"
--
1.7.4.1


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