Messages in this thread | | | Date | Thu, 29 Aug 2013 10:19:03 -0400 (EDT) | From | Alan Stern <> | Subject | Re: Memory synchronization vs. interrupt handlers |
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On Wed, 28 Aug 2013, H. Peter Anvin wrote:
> On 08/28/2013 12:16 PM, Alan Stern wrote: > > Russell, Peter, and Ingo: > > > > Can you folks enlighten us regarding this issue for some common > > architectures? > > > > On x86, IRET is a serializing instruction; it guarantees hard > serialization of absolutely everything.
That answers half of the question. What about the other half? Does the CPU automatically serialize everything when it takes an interrupt?
> I would expect architectures that have weak memory ordering to put > appropriate barriers in the IRQ entry/exit code.
Then would it be acceptable to mention this in the memory-barriers.txt file?
Alan Stern
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