Messages in this thread | | | From | Keith Packard <> | Subject | Re: [PATCH 4/5] drm/i915: Add async page flip support for IVB | Date | Wed, 24 Jul 2013 13:26:32 -0700 |
| |
Daniel Vetter <daniel@ffwll.ch> writes:
> Matching tiling modes is actually already a requirement on gen4+ (since > the tiling bit and the linear/tiled offset registers can't be changed with > a MI_DISPLAY_FLIP command).
Async flip has a harder requirement -- you must use X tiling, both before and after the flip. Oh, and async flips require a 32KB aligned buffer, which I'm not actually checking for. Not sure how to
> But atm we fail to check that in the common > code, so imo better to move that to there. > > We already check for matching strides in common code, so with the tile > check added we could drop this all here.
I don't see a requirement for matching stride and tile parameter in the MI_DISPLAY_FLIP docs for synchronous operations, at least on DevGT+. Is the common code too restrictive?
-- keith.packard@intel.com [unhandled content-type:application/pgp-signature] | |