Messages in this thread | | | Date | Tue, 2 Jul 2013 13:43:38 +0300 | From | Felipe Balbi <> | Subject | Re: [PATCHv2] drivers: spi: Add qspi flash controller |
| |
On Tue, Jul 02, 2013 at 11:17:18AM +0100, Mark Brown wrote: > On Tue, Jul 02, 2013 at 12:44:04PM +0300, Felipe Balbi wrote: > > On Tue, Jul 02, 2013 at 10:32:47AM +0100, Mark Brown wrote: > > > > Does this hardware really support anything other than 8 bits per word? > > > There is no code in the driver which pays any attention to the word > > > size... > > > the HW has a 128-bit shift register ;-) but driver doesn't look > > complete. > > That's not the issue - remember that SPI specifies big endian byte > ordering for words on the bus so things will need to be reordered by the > hardware for anything except 8 bits.
right, the driver is far from being complete. In fact this driver is quite buggy, if you look here :
> +static int dra7xxx_qspi_start_transfer_one(struct spi_master *master, > + struct spi_message *m) > +{ > + struct dra7xxx_qspi *qspi = spi_master_get_devdata(master); > + struct spi_device *spi = m->spi; > + struct spi_transfer *t; > + int status = 0; > + int flags = 0; > + > + /* setup command reg */ > + qspi->cmd = 0; > + qspi->cmd |= QSPI_WLEN(8);
Sourav hardcodes wordlenght to 8-bits, and yet he enables 8, 16 and 32-bits per word.
> + qspi->cmd |= QSPI_EN_CS(0);
he's also hardcoding the chipselect line which should be take from m->spi->chip_select
> + qspi->cmd |= 0xfff;
and he's hardcoding the frame length to 4096 frames!!
This is all buggy.
-- balbi [unhandled content-type:application/pgp-signature] | |