Messages in this thread | | | Date | Tue, 16 Jul 2013 16:39:32 -0700 | Subject | Re: [PATCH v5] x86: make sure IDT is page aligned | From | Yinghai Lu <> |
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On Tue, Jul 16, 2013 at 3:16 PM, H. Peter Anvin <hpa@zytor.com> wrote: > On 07/16/2013 03:13 PM, Yinghai Lu wrote: >> >> ok, then should change >> >>> +/* No need to be aligned, but done to keep all IDTs defined the same way. */ >>> +gate_desc trace_idt_table[NR_VECTORS] __page_aligned_bss; >> >> ==> >> >>> +/* Only need to be cacheline aligned, but keep all IDTs defined the same way to be page aligned. */ >>> +gate_desc trace_idt_table[NR_VECTORS] __page_aligned_bss; > > It doesn't need to be cacheline aligned, either, to the best of my > knowledge. The former comment is more correct.
ok. so the old code is just for optimization to keep it cacheline aligned?
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