Messages in this thread | | | Date | Tue, 11 Jun 2013 10:30:48 +0300 | From | Peter De Schrijver <> | Subject | Re: [PATCH V3 3/4] ARM: dts: tegra: Correct PCIe entry |
| |
On Mon, Jun 10, 2013 at 09:55:12PM +0200, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Wed, Jun 05, 2013 at 12:27:31AM +0530, Jay Agarwal wrote: > [...] > > @@ -29,7 +29,7 @@ > > ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ > > 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ > > 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ > > - 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ > > + 0x81000000 0 0 0x02000000 0 0x00100000 /* downstream I/O */ > > 0x82000000 0 0x20000000 0x20000000 0 0x10000000 /* non-prefetchable memory */ > > 0xc2000000 0 0x30000000 0x30000000 0 0x10000000>; /* prefetchable memory */ > > That increases the I/O region size from 64 KiB to 1 MiB. Why is that > necessary? I/O operations can only address 64 KiB, so I don't think > adding more makes any sense.
At least PCI allows 32bit I/O addresses. No idea if anyone uses them though.
Cheers,
Peter.
| |