Messages in this thread | | | Date | Tue, 14 May 2013 13:04:50 -0700 (PDT) | Subject | Re: [PATCH v2] net/macb: fix ISR clear-on-write behavior only for some SoC | From | David Miller <> |
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From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Date: Tue, 14 May 2013 18:24:50 +0200
> On 15:00 Tue 14 May , Nicolas Ferre wrote: >> Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR) >> introduces clear-on-write on ISR register. This behavior is not always >> implemented when using Cadence MACB/GEM and is breaking other platforms. >> We are using the Design Configuration Register 1 information and a capability >> property to actually activate this clear-on-write behavior on ISR. >> >> Reported-by: Hein Tibosch <hein_tibosch@yahoo.es> >> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> > Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Applied, thanks.
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