Messages in this thread | | | Date | Mon, 15 Apr 2013 18:59:16 -0500 | From | Rob Herring <> | Subject | Re: [RFC PATCH 1/3] pstore-ram: use write-combine mappings |
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On 04/15/2013 05:21 PM, Colin Cross wrote: > On Wed, Apr 10, 2013 at 6:30 AM, Rob Herring <robherring2@gmail.com> wrote: >> On 04/09/2013 10:53 PM, Colin Cross wrote: >>> On Tue, Apr 9, 2013 at 8:08 PM, Rob Herring <robherring2@gmail.com> wrote: >>>> From: Rob Herring <rob.herring@calxeda.com> >>>> >>>> Atomic operations are undefined behavior on ARM for device or strongly >>>> ordered memory types. So use write-combine variants for mappings. This >>>> corresponds to normal, non-cacheable memory on ARM. For many other >>>> architectures, this change should not change the mapping type. >>> >>> This is going to make ramconsole less reliable. A debugging printk >>> followed by a __raw_writel that causes an immediate hard crash is >>> likely to lose the last updates, including the most useful message, in >>> the write buffers. >> >> It would have to be a write that hangs the bus. In my experience with >> AXI, the bus doesn't actually hang until you hit max outstanding >> transactions. > > I've seen many cases where a single write to device memory in an > unclocked slave will completely and instantly hang all cpus, and the > next write will never happen. > >> I think exclusive stores will limit the buffering, but that is probably >> not architecturally guaranteed. >> >> I could put a wb() in at the end of persistent_ram_write. >> >>> Also, isn't this patch unnecessary after patch 3 in this set? >> >> It is still needed in the main memory case to be architecturally correct >> to avoid multiple mappings of different memory types and exclusive >> accesses to device memory. At least on an A9, it doesn't really seem to >> matter. I could remove this for the ioremap case. > > According to my reading of the latest ARM ARM (Issue C, section > A3.5.7), and Catalin's excellent explanation > (http://lists.linaro.org/pipermail/linaro-dev/2012-February/010239.html), > it is no longer considered unpredictable to have both cached and > non-cached mappings to the same memory, as long as you use proper > cache maintenance between accessing the two mappings. > > In pstore_ram the cached mapping will never be accessed (and we don't > care about speculative accesses), so no cache maintenance is > necessary. I don't see any need for this patch, and I see plenty of > possible problems.
Exclusive accesses still have further restrictions. From section 3.4.5:
• It is IMPLEMENTATION DEFINED whether LDREX and STREX operations can be performed to a memory region with the Device or Strongly-ordered memory attribute. Unless the implementation documentation explicitly states that LDREX and STREX operations to a memory region with the Device or Strongly-ordered attribute are permitted, the effect of such operations is UNPREDICTABLE.
Given that it is implementation defined, I don't see how Linux can rely on that behavior.
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